Ethereum Blockchain Network Implementation for IoT Platform

Internet of things (IoT) is becoming increasingly important and ubiquitous in home and industries. It makes object a part of the Internet and fuses the digital and physical world together. However, if not properly secured, IoT device can be vulnerable to tampering that can change the content of the data stored in the network. Blockchain, a technology used in cryptocurrency, can be used for addressing the security and privacy challenges in IoT. Blockchain can be beneficial to IoT by adding more security layer and reducing dependency on a central authority. This paper proposed to develop a blockchain based platform for IoT application. Blockchain technology can be utilized to provide a decentralized network, creating a more secured IoT system. The proposed blockchain network will be based on Ethereum blockchain network allowing the use smart contract application for management of IoT devices. Experiment is conducted to show the feasibility of the blockchain based platform. The proposed blockchain based platform is capable of managing several IoT devices connected to the network

Accelerating Extreme Learning Machine on FPGA by Hardware Implementation of Given Rotation - QRD

Currently, Extreme Learning Machine (ELM) is one of the research trends in the machine learning field due to its remarkable performances in terms of complexity and computational speed. However, the big data era and the limitations of general-purpose processor cause the increasing of interest in hardware implementation of ELM in order to reduce the computational time. Hence, this work presents the hardware-software co-design of ELM to improve the overall performances. In the co-design paradigm, one of the important components of ELM, namely Given Rotation-QRD (GR-QRD) is developed as a hardware core. Field Programmable Gate Array (FPGA) is chosen as the platform for ELM implementation due to its reconfigurable capability and high parallelism. Moreover, the learning accuracy and computational time would be used to evaluate the performances of the proposed ELM design. Our experiment has shown that GR-QRD accelerator helps to reduce the computational time of ELM training by 41.75% while maintaining the same training accuracy in comparison to pure software of ELM

FPGA-Assisted Assertion-Based Verification Platform

In this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the firstin-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time

Esophagus Detection for Halal Classification in SYCUT

According to the Islamic Law, one of the procedures in halal slaughtering of chicken is the step of severing the trachea, esophagus and both the carotid arteries and jugular veins to accelerate the chicken’s bleeding and death. Syariah Compliance Automated Chicken Processing System (SYCUT) uses the Vision Inspection Technology to detect and classify whether a chicken is halal or not. The lack of quality and halal assurance in chicken processing industry made it a need to produce such technology. The system implements image processing techniques and artificial intelligence approach, particularly the Viola and Jones object detection framework for esophagus detection. The results of the experiment from two different sites (Az-Zain and 3P) are 81.8% and 55% respectively. The detection module of those two sites show results of 95.6% and 93.5% which are the accuracy as good as human personnel

Advance devices using piezoelectric harvesting energy

In this paper, an innovative method of energy harvesting sliding door design and develop a piezoelectric device in working with Programmable Interface Controller. The devices arranged in series connection and equipped in a sliding door hinges. The PIC microcontroller system modified by Proteus software which is a software tool used to simulate the programming source code, electronic circuits and mechanical systems to compare their performance with actual hardware system. To complete energy harvesting system, the microcontroller used to monitor system performance in terms of simulation input trigger

A new metaheuristic algorithm for global optimization over continuous search space

A new metaheuristic global optimization method for non-linear and nondifferentiable problems is proposed and described in this article It is a swarm-based method which uses spherical boundaries in a vector search-space to explore for the optimal solution Having a few numbers of parameters to be adjusted being robust and fast needing less memory storage size and capability of escaping from local optima are the main features of this new method To analyze and evaluate the capability of this novel method ten benchmark functions are chosen and the results are compared with two existing optimization methods which are Differential Evolution and Particle Swarm Optimization Comparisons are made based on the consistency in obtaining optimal solutions computation time and convergence profile Results show the capability of the proposed method in finding a proper and fast solution and also escaping from local optima of the problem solution-spac

Oversampling based on data augmentation in convolutional neural network for silicon wafer defect classification

Silicon wafer defect data collected from fabrication facilities is intrinsically imbalanced because of the variable frequencies of defect types. Frequently occurring types will have more influence on the classification predictions if a model gets trained on such skewed data. A fair classifier for such imbalanced data requires a mechanism to deal with type imbalance in order to avoid biased results. This study has proposed a convolutional neural network for wafer map defect classification, employing oversampling as an imbalance addressing technique. To have an equal participation of all classes in the classifier's training, data augmentation has been employed, generating more samples in minor classes. The proposed deep learning method has been evaluated on a real wafer map defect dataset and its classification results on the test set returned a 97.91% accuracy. The results were compared with another deep learning based auto-encoder model demonstrating the proposed method, a potential approach for silicon wafer defect classification that needs to be investigated further for its robustness

A review of breast boundary and pectoral muscle segmentation methods in computer-aided detection/diagnosis of breast mammography

Mammography can be considered as the current gold standard for detecting early signs of breast cancer and is in wide use throughout the world. As confirmed by many studies, breast cancer screening using mammography can reduce breast cancer-related mortality by 30–70%. However, although the interpretation of mammography images by a second reader has been shown to increase the cancer detection rate, this practice is not widespread due to the cost associated. As a result, computer-aided detection/diagnosis (CAD) of breast mammography has been gaining popularity with various studies illustrating the positive effects of using computers in detecting early breast cancer signs by providing the radiologists with a second opinion with most of these CAD systems requiring the breast outline and pectoral muscle regions (in images acquired using Medio-Lateral-Oblique view) to be segmented from mammograms prior to the classification. This paper discusses recent developments and methods proposed for segmenting the breast and pectoral muscle regions and compares the performance and shortcomings of different approaches grouped together based on the techniques used. While it is arduous to compare these methods using comparative analysis, a set of common performance evaluation criterion is defined in this study and various methods are compared based on their methodology and the validation dataset used. Although many methods can achieve promising results, there is still room for further development, especially in pre-processing and image enhancement steps where most methods do not take the necessary steps for ensuring a smooth segmentation of boundaries. In this paper, the most effective pre-processing, image enhancement and segmentation concepts proposed for breast boundary and pectoral muscle segmentation are identified and discussed in hopes of aiding the readers with identifying the best possible solutions for these segmentation problems

FPGA-Assisted assertion-based verification platform

In this paper, field programmable gate array (FPGA)-assisted verification platform is devised to enhance the assertion-based verification methodology to address the issues of high demand of integrated circuit with the advanced features to be delivered to market within tight Time-To-Market. The concept of SystemVerilog Assertion (SVA) checker generator is introduced to translate non-synthesizable verification coding into hardware so-called assertion checker in Verilog. A lookup table, which comprises of SVA operators mapped to their corresponding synthesizable Verilog coding was developed to generate assertion checker, which produces a single bit 1 when the assertion fails. Collection module implemented using a memory block and an arbiter was devised to be simple and fast enough to collect assertion results from the assertion checker. Since assertion checker can produce assertion result at any time, an arbiter is required to act as an interface between assertion checker and collection module. Case studies have been conducted on the proof-of-concept designs, which are the firstin-first-out (FIFO), up-down counter and Context Adaptive Variable Length Coding (CAVLC) to evaluate the effectiveness of the proposed FPGA-assisted verification platform. In the case studies, we have shown that the proposed FPGA-assisted verification platform works correctly. Besides, we also evaluated the method in area utilizations (ALMs). It has been proven that simulation-based verification time can be reduced for as much as 50% for complexity of VLSI design. Thus, implementing assertions using hardware such as FPGA becomes a solution to alleviate issue of long simulation time